1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, in which a microscopic line and space pattern is formed.
2. Description of the Related Art
A line-and-space wiring pattern is well known and includes a plurality of lines each of which has a predetermined width and which are arranged with a predetermined space or interval. The following two methods are available for forming the line-and-space wiring pattern. In one method, a wiring material film is patterned, whereas, in the other method, a trench is formed in an insulating film further formed on a semiconductor substrate and is filled with a wiring pattern material. In the former method, a film to be processed which is a conductive film is patterned into a wiring pattern using a mask having the same pitch as the line-and-space. In the latter, a film to be processed which is an insulating film is patterned using a mask with the same pitch as the line-and-space, so that a trench is formed. The trench is filled with a wiring material and thereafter, an upper surface of the semiconductor substrate is polished by a chemical mechanical polishing (CMP) method, whereupon a wiring pattern is formed.
An optically readable mask pattern is used in an exposure technique of the photolithography both in the above-described two methods. Accordingly, whether a desired pitch of the line-and-space pattern can be obtained depends upon the precision of the exposure technique. However, microfabrication has recently been progressing at an accelerating pace in the semiconductor fabrication technique. Under these circumstances, the line-and-space pattern is required to have a pitch of not more than a limit of the exposure technique.
U.S. Pat. No. 6,638,441 proposes a semiconductor fabricating method in which a line-and-space pattern with a pitch equal to one third of an original pitch is formed by use of the photolithography technique. The disclosed fabricating method includes the following steps. Firstly, a photoresist layer formed on a semiconductor substrate is patterned and thereafter, a first layer is formed on the photoresist layer. The first layer is etched back so that the substrate is exposed. Subsequently, a second layer is formed on the substrate including the upper surface of the first layer. The second layer is etched back so that the photoresist layer and the first layer are exposed. Thereafter, the photoresist layer is removed. A third layer is then formed on the substrate including the upper surface of the first layer. The third layer is etched back so that the substrate is exposed. Subsequently, a fourth layer is formed on the first layer and then etched back so that the first layer is exposed. Thereafter, the second and third layers are removed.
However, the above-described fabricating method necessitates a large number of steps and accordingly a long fabricating time. As a result, the yield is reduced and the fabricating cost is increased.